The invention relates to a field-effect-controllable, vertical semiconductor component, including a semiconductor body having at least one drain region of a first conduction type, at least one source region of the first conduction type, at least one body region of the second conduction type separating the drain regions and source regions from one another, and at least one gate electrode insulated from the entire semiconductor body by a gate oxide. The invention also relates to a method for producing the semiconductor component and a monolithically integrated half bridge.
Field-effect-controllable semiconductor components of that kind are, for example, MOS field-effect transistors (MOSFETs). Such MOSFETs have been known for a long time and are described, for example, in the Siemens-Datenbuch [Data Manual] 1993/94 SIPMOS-Halbleiter, Leistungstransistoren und Dioden [SIPMOS Semiconductors, Power Transistors and Diodes], pp. 29 ff. FIG. 4 on page 30 of that data manual shows the basic layout of a power transistor of that kind. The transistor shown there is a vertical n-channel SIPMOS transistor. In such a transistor, the n+ substrate serves as a carrier with the drain metallizing beneath it. Above the n+ substrate, an nxe2x88x92epitaxial layer follows, which is variously thick and correspondingly doped depending on the depletion voltage. The gate over that, made of n+ polysilicon, is embedded in insulating silicon dioxide and acts as an implantation mask for the p well and the n+ source zone. The source metallizing covers the entire structure and connects the individual transistor cells of the chip in parallel. Further details of that vertically constructed power transistor can be found on pages 30 ff. of the aforementioned data manual.
A disadvantage of such a configuration is that the on-state resistance Ron of the drain-to-source load path increases with increasing dielectric strength of the semiconductor component, since the thickness of the epitaxial layer necessarily increases. At 50 V, the on-state resistance Ron per unit of surface area is approximately 0.20 xcexa9 mm2, and rises at a depletion voltage of 1000 V to a value of approximately 10 xcexa9 mm2, for instance.
In general a distinction is made between lateral and vertical MOSFETs. In contrast to lateral MOSFETs, vertical MOSFETs have a substantially vertical current flow direction. That causes the current to flow from the front side of the wafer to the rear side of the wafer. In vertical MOSFETs of that generic type, the source and gate terminals are located on the front side of the wafer, while the drain terminal is contacted through the rear side of the wafer.
Vertical MOSFETs have the advantage over lateral MOSFETs of being integratable on the semiconductor chip in a space-saving way, and therefore the components can be manufactured less expensively. Moreover, vertical transistors, in comparison with lateral structures, under the same process-related peripheral conditions or the same cell concepts, have a turn-on resistance Ron that is about 50% less. The result thereof is that at the same turn-on resistance, the chip area in vertical transistors is only about half as large. The wafer costs for an intelligent vertical transistor are approximately 80% of those for a corresponding lateral transistor, such as an updrain transistor.
The processes which are currently used for vertical transistors make it possible to realize multichannel high-side switches. In those high-side switches, the drain terminal is on the rear side of the chip. It is currently possible to realize monolithically integrated multichannel low-side switches only with lateral or updrain structures.
It is accordingly an object of the invention to provide a field-effect-controllable, vertical semiconductor component, a method for producing the same and a monolithically integrated half bridge, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a field-effect-controllable vertical semiconductor component, comprising a semiconductor body having: front and rear wafer sides; at least one drain region of a first conduction type; at least one source region of the first conduction type; at least one body region of a second conduction type between the at least one drain region and the at least one source region; at least one gate electrode; and a gate oxide insulating the at least one gate electrode from the entire semiconductor body; a gate terminal and a drain terminal disposed on the front wafer side; and a source terminal disposed on the rear wafer side.
The invention has the advantage in particular of permitting the source contact on the rear side of the wafer to be secured directly to a device housing, without any insulating layer. The specific heat resistance is less as a result, which leads to improved heat dissipation through the rear side of the wafer.
In accordance with another feature of the invention, there are provided trenches, in which the gate electrodes and the gate oxide are located. Placing the gate electrodes in vertical trenches makes it possible on one hand to achieve further space savings in the vertical MOSFETs. On the other hand, MOSFETs with high breakdown voltages can advantageously be realized with a simultaneously low turn-on resistance Ron.
In accordance with a further feature of the invention, doped polysilicon is used as a material for the gate electrode, because in process terms it is simple to manipulate and it has good conductivity.
In accordance with an added feature of the invention, the gate oxide is thermally produced silicon dioxide, which is qualitatively quite valuable and is simple to manipulate in process terms.
In accordance with an additional feature of the invention, the gate oxide in the vicinity of the drain drift region is substantially thicker than in the vicinity of the body region and the source region. As a result, the depletion properties of the MOSFETs of the invention are additionally improved.
In accordance with yet another feature of the invention, there are provided ion-implanted contact regions embedded in the drain regions. These contact regions have a very high dopant concentration. This assures an ohmic contact between the contact regions and the drain terminals. The exact dopant dose can advantageously be determined through the use of ion implantation, and thus a defined dopant concentration of the contact region can be generated.
In accordance with yet a further feature of the invention, to avoid latch effects, the body regions are connected with low impedance to the source region.
In accordance with yet an added feature of the invention, there are provided first connection regions having the same conduction type as the at least one body region and a very high dopant concentration, the first connection regions connecting the at least one body region to a surface of the front wafer side, and a bonding contact wire short-circuiting the connection regions on the wafer surface to the source terminal.
In accordance with yet an additional feature of the invention, there are provided first and second connection regions of the same conduction type and a very high dopant concentration, the first and second connection regions each connecting a respective one of the at least one body region and the at least one source region to a surface of the front wafer side, and a connecting metallizing on the wafer surface short-circuiting the first and second connection regions.
In accordance with again another feature of the invention, there are provided further trenches filled with conductive material and short-circuiting the at least one body region and the at least one source region.
In accordance with again a further feature of the invention, there is provided a monolithically integrated half bridge including a low-side MOSFET according to the invention and a high-side MOSFET of the known type.
With the objects of the invention in view, there is also provided a production method for a field-effect-controllable vertical semiconductor component, which comprises the following steps: implanting one of boron and aluminum in a semiconductor body having a front wafer side, a rear wafer side and a source region, to produce a body region by an ensuing suitable temperature process; epitaxially growing an n-doped drain region on the body region defining a surface of the drain region; introducing contact regions into the drain regions near the surface by ion implantation; then applying and structuring a thick oxide to serve as a mask for trench etching; anisotropically etching trenches from the front wafer side to a depth of the source region defining walls of the trenches; growing thermal silicon dioxide as a gate oxide on the walls of the trenches; filling the trenches with n+-doped polysilicon and then etching away excess polysilicon; depositing a field oxide on the front wafer side, and etching away excess field oxide at the contact regions of the drain regions; contacting the contact regions with aluminum; and metallizing the rear wafer side over a large surface area with aluminum.
In accordance with a concomitant mode of the invention, there is provided a production method for a field-effect-controllable vertical semiconductor component, which comprises depositing BPSG as the field oxide.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a field-effect-controllable, vertical semiconductor component, a method for producing the same and a monolithically integrated half bridge, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.